The development of electronic devices and electronic component devices around digital home appliances or portable information terminals including multimedia devices has been advancing in recent years. Along with the advancement in the development of devices, semiconductor devices used in these electronic devices and the like have been increasingly required to have a smaller size, more functions, higher performances, and the like. In order to meet such a demand, a System on Chip (SOC) technology for integrating advanced system functions in a single chip has been receiving attention. In the SOC, a system which has been realized on a board in the past is realized on a single semiconductor chip (typically, a silicon chip). The SOC is quite advantageous because of lower power consumption, high performance, and reduction in mounting area.
Meanwhile, the prolonged development period for SOCs and the development risk associated with integration of various system functions into a single chip have been bottlenecks. For this reason, a System in Package (SIP) technology has been receiving attention, which has a possibility of realizing the functions equivalent to those of the SOC in a short period of time and also at low costs. Such an SIP is also called a System on Module. The SIP achieves a system by mounting multiple LSI chips (an active device such as a CPU, a passive device such as a DRAM, and the like) in a single package.
As one of the forms of semiconductor devices to which such an SIP technique is applied, there is a form which is a so called “multiple chip module (MCM).” The MCM is provided in various forms, one of which uses an interposer. In the MCM using an interposer, multiple chips are mounted on an interposer in parallel, and the interposer with the multiple chips is further mounted on a mounting wiring board (e.g., an organic substrate using an epoxy resin, polyimide resin or the like for a base member). Specifically, the chips are electrically connected to each other via the interposer and wiring board.
In addition, as the next generation package to be integrated into the aforementioned semiconductor device, a silicon interposer has been developed. The silicon interposer has a coefficient of thermal expansion (CTE) which is almost the same as that of a silicon chip to be mounted thereon. Accordingly, when the silicon interposer is used, there is substantially no thermal expansion mismatch between the interposer and the silicon chip. Thus, use of such a silicon interposer is advantageous in that the reliability in terms of temperature cycling test improves. In addition, even when a Low-K device (semiconductor device using a low-dielectric material for an interlayer insulating film) is mounted in this case, no damage is given thereto and there is an advantage that a semiconductor device to which a “strained silicon” technique is applied can be supported. In addition, a silicon substrate is advantageous in that fine wirings are easily formed because the silicon substrate is excellent in flatness as compared with an organic substrate (resin substrate).
Meanwhile, an active device such as a CPU (“logic” chip) to be integrated into the semiconductor device generates a large amount of heat during operation because of high-speed signal transmission required for the active device due to an increase in the density and functionality (higher clock frequency) of the active device. For this reason, unless the device temperature during operation is forcibly lowered, not only the active device may fail to deliver the performance as a “logic” element, but also the chip may break down in some cases. In order to prevent such an incident, a heat spreader (plate-like heat dissipating member made of a metal) for releasing the heat generated during the operation of the chip into the atmosphere is often arranged on the chip.
An example of the technique relating to the related art is described in Japanese Laid-open Patent Publication No. 2004-71719. The publication discloses a technique for mounting an electronic circuit device on a mounting board, the electronic circuit device including multiple semiconductor chips mounted on an interposer. In addition, another technique relating to the technique disclosed in the publication is described in Japanese Laid-open Patent Publication No. 2004-79745. This publication discloses a technique in which the rear surface of the silicon substrate forming the interposer is receded in such a manner that a penetrating conductive layer can protrude from the rear surface thereof, and a bump electrode made of solder or the like is formed on the leading edge of the penetrating conductive layer protruding from the rear surface.
In a case where a silicon interposer is used in a semiconductor device to which the SIP technique is applied, there are the above-described advantages in various points with no particular problems in a relationship with the chip to be mounted thereon. This is because the silicon interposer has a coefficient of thermal expansion (CTE) which is almost the same as that of the silicon chip to be mounted thereon. However, in a relationship with an organic substrate (build-up board, motherboard or the like) on which the silicon interposer is mounted, the following problems exist.
Specifically, a large difference between the CTE of the silicon interposer and the CTE of the organic substrate leads to a problem that the reliability in terms of temperature cycling test is reduced in a case where the silicon interposer is mounted on the organic substrate because of a large thermal expansion mismatch between the silicon interposer and the board. The problem is more apparent when the silicon interposer is large in size (e.g., 20 mm×20 mm or larger).
Since the silicon interposer is placed between the chips and the organic substrate, the size of the silicon interposer needs to be larger than a size obtained by adding up the sizes of the individual chips to be mounted thereon in a plan view. More specifically, since the required size of the interposer is relatively large, the amount of warpage caused by a thermal stress generated due to a difference between the CTE of the interposer and the CTE of the substrate also increases in accordance with the size of the interposer. This increase in the warpage causes a problem that a crack occurs in a terminal connection portion in some cases (reduction in the reliability in terms of temperature cycling test).
In addition, in a case of a module board on which a passive device such as a DRAM (“memory” chip) is mounted together with a “logic” chip, a heat spreader is thermally coupled to the “logic” chip in general as described above, but the heat spreader is thermally coupled also to the “memory” chip in the structure of this module (in other words, the chips are not thermally isolated from each other). In addition, the amount of heat generated from the “logic” chip is much larger than the amount of heat generated from the “memory” chip during operation. For this reason, the heat generated from the “logic” chip is easily conducted to the “memory” chip via the heat spreader. In addition, a DRAM is relatively weak against heat. Hence depending on the amount of heat conducted to the memory chip, the conducted heat leads to a problem which causes the “memory” chip to malfunction.
In addition, because of the presence of the heat spreader to be shared between the chips on the module board, there is a limitation that a “logic” chip with a lower grade (i.e., less power consumption but lower performance) has to be used in consideration of the influence of heat generation on the “memory” chip even though use of a chip with higher performance as the “logic” chip is desired.
The above-described problems in the related art are not necessarily unique to the case where a silicon interposer is used and mounted on an organic substrate. Regardless of whether or not “silicon” or “resin” is used, the problems may occur likewise in a case where an interposer has a predetermined CTE in a relationship with the chip to be mounted thereon, and a wiring board having a CTE different from the CTE of the interposer to a large extent in a relationship with the interposer is used.